It is well known in the communication arts that a transmit (Tx) buffer is required for both wired and wireless communications systems to interface the transmit path signal to the outside environment. In many cases, the transmit buffer is required to apply a variable gain to the transmit signal in order to increase or reduce the amplitude of the output signal. One such case occurs when the transmitted signal is part of an amplitude modulated communication system and the transmit buffer itself is used to implement the amplitude modulation function. The signal to noise ratio (SNR) requirements of such Tx buffers in most systems are extremely strict, meaning that any amplitude control circuitry should contribute no more than negligible noise to the buffer output. The reverse isolation (which can also be considered gain accuracy at low gain levels) of such transmit buffers is also an important concern. In addition, the current consumption requirements for these transmit buffers are limited such that any gain control scheme cannot ‘bum’ or waste current in order to meet the power consumption budget and the strict signal to noise requirements stated above.
A prior art digitally controlled near class E power amplifier designed for the Bluetooth wireless communication standard provides a limited number of bits for amplitude control (e.g., only 3.5 bits of amplitude control) and is used for power regulation of the transmitted constant envelope RF output. The previous lowest reported power consumption for a prior art GSM transmit chain, having no power control, is 17 mW with −7 dBm output power. The design for such a system has a transmitted power efficiency of 2.7% for an output power of 0 dBm.
There exist in the prior art multiple transmit chain architectures for transforming a digitally encoded bit stream into an RF modulated waveform at a power level suitable for transmission. The transmit power level for a cellular transceiver integrated circuit (IC) is typically around 3 dBm for interfacing with external power amplifiers (PAs). This output power level, however, is not constant in amplitude-modulated standards, such as EDGE, and must be controlled with appropriate variable-gain circuitry. Typical prior art architectures, such as single-sideband upconversion, perform digital-to-analog conversion on-chip and employ a variable gain pre-power amplifier (PPA) to transmit the required signal at the desired power level. In these architectures, the overall power consumption of the transmit chain, including all the DAC and variable gain buffer components, is at least 50 mW which is a relatively high amount of power. It is desirable to be able to reduce the power consumption of the transmit chain significantly.
All digital CMOS pre-power amplifiers exist in the art. A pre-power amplifier is designed to generate an output signal having desired waveform characteristics that is fed into the final power output stage before being transmission over the wireless channel. In a CMOS RF transmitter, the pre-power amplifier (typically the last buffer stage) functions as an RF digital to analog converter (DAC) followed by an analog high power buffer. The pre-power amplifier power is varied by switching the transistors in the PPA switch array on and off. This, however, causes the output load to vary as well. The changes in impedance between full on and off can be extreme resulting in very high impedance mismatch between the source and the load. The impedance mismatch phenomenon does not affect the performance of the PPA but it severely impact the performance of the SAW filter that follows the PPA or the performance of the power amplifier if no SAW filter is used.
There is thus a long felt need for a pre-power amplifier incorporating a load compensation circuit that is able to maintain a nearly constant output impedance across the entire output range of the pre-power amplifier from the minimum code to the maximum code. In addition, the pre-power amplifier should be able to be implemented using digital CMOS processes.